Department of Electronics and Communication Engineering
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
The Department of Electronics and Communication Engineering has been established in the year 1980 and a full time M. Tech. program started in the year 1992. The department is recognised as the Research Centre by VTU, Belagavi in the year 2002 and attained autonomous status in the year 2007. Thus the department has shown its progress in various dimensions. The present intake for UG is 120 and for PG, it is 18. The UG program has been accredited thrice and PG program has been accredited twice by National Board of Accreditation, New Delhi. With the vision of fostering excellence in the field of Electronics and Communication Engineering, we provide quality education through the state-of-the-art curriculum, effective teaching learning process, encouragement to innovation, inculcating research culture and building team spirit among students.
Many of our UG and PG alumni are holding key positions in private and public sector organizations, R&D organizations and some of them are also the successful entrepreneurs. With no complacency, we strive hard to achieve greater laurels in the years to come. There are well qualified and experienced faculty with 50% doctorates in the areas of Signal Processing, Communication Systems, VLSI Design and Embedded Systems and most of the remaining pursuing Ph.D. There are well equipped classrooms and laboratories with industry standard software tools such as Cadence 6, Lab view 14.0, Xilinx 14.7i, Keil 5, MATLAB 2014 B, high end FPGA kits, ARM boards and Software Defined Radio kits. There are several ongoing R&D funded projects worth total of above Rs. 70 lakh. Internship program and industry sponsored projects are carried out by students.
- Year of Establishment: 1980
- Head of Department: Prof. Dr. Shreedhar A Joshi, Professor and Head, Department of Electronics and Communication Engineering , Dharwad-02
- NBA Accreditation Status: Academic Years 2020-2021, 2021-2022 and 2022-2023 i.e. up to 30.06.2023; Further accredited for Academic Year 2023-24, 2024-25 and 2025-26, i.e., upto 30/06/2026.
- Current Intake: 120
- Phone Number: (0836) 244-7465
Vision of the Department:
Fostering excellence in the field of Electronics & Communication Engineering, showcasing innovation, research and performance with continuous Industry – Institute Interaction with the blend of Human values.
Mission of the Department:
- M1: To provide quality education in the domain of Electronics & Communication Engineering through state of the art curriculum, effective teaching learning process and the best of laboratory facilities.
- M2: To encourage innovation, research culture and team work among students.
- M3: Interact and work closely with industries and research organizations to accomplish knowledge at par.
- M4: To train the students for attaining leadership with ethical values in developing and applying technology for the betterment of society and sustaining the global environment.
PEOs & POs
Programme Educational Objectives(PEOs)
UG – Electronics & Communication Engineering: PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
The Graduates, after a few years of Graduation will be able to:
|PEO 1||Apply the latest in-depth knowledge in the field of Electronics and Communication Engineering with Mathematical applications to address real life challenges.|
|PEO 2||Exhibit the confidence for independent working and / or spirit to work cohesively with group.|
|PEO 3||Readily be accepted by the Industry globally.|
|PEO 4||Develop design skills, fault diagnosis skills, communication skills and create research orientation.|
|PEO 5||Inculcate professional, social ethics and to possess awareness regarding societal responsibility, moral and safety related issues|
UG – Electronics & Communication Engineering: PROGRAM OUTCOMES (POs)
Engineering Graduates will be able to:
|PO||Short Title of the PO||Description of the Programme Outcome (PO) |
Engineering Graduates will be able to:
|PO-1||Engineering knowledge||Apply the knowledge of mathematics, science, engineering fundamentals, and an engineering specialisation to the solution of complex engineering problems.|
|PO-2||Problem analysis||Identify, formulate, review research literature, and analyze complex engineering problems reaching substantiated conclusions using first principles of mathematics, natural sciences, and engineering sciences.|
|PO-3||Design/development of solutions||Design solutions for complex engineering problems and design system components or processes that meet the specified needs with appropriate consideration for the public health and safety, and the cultural, societal, and environmental considerations.|
|PO-4||Conduct investigations of complex problems||Use research-based knowledge and research methods including design of experiments, analysis and interpretation of data, and synthesis of the information to provide valid conclusions.|
|PO-5||Modern tool usage||Create, select, and apply appropriate techniques, resources, and modern engineering and IT tools including prediction and modeling to complex engineering activities with an understanding of the limitations.|
|PO-6||The engineer and society||Apply reasoning informed by the contextual knowledge to assess societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to the professional engineering practice.|
|PO-7||Environment and Sustainability||Understand the impact of the professional engineering solutions in societal and environmental contexts, and demonstrate the knowledge of, and need for sustainable development.|
|PO-8||Ethics||Apply ethical principles and commit to professional ethics and responsibilities and norms of the engineering practice.|
|PO-9||Individual and team work||Function effectively as an individual, and as a member or leader in diverse teams, and in multidisciplinary settings.|
|PO-10||Communication||Communicate effectively on complex engineering activities with the engineering community and with society at large, such as, being able to comprehend and write effective reports and design documentation, make effective presentations, and give and receive clear instructions.|
|PO-11||Project Management and Finance||Demonstrate knowledge and understanding of the engineering and management principles and apply these to one’s own work, as a member and leader in a team, to manage projects and in multidisciplinary environments.|
|PO-12||Life-long Learning||Recognize the need for, and have the preparation and ability to engage in independent and life-long learning in the broadest context of technological change.|
Programme Specific Outcomes (PSOs)
UG – Electronics and Communication: PROGRAM SPECIFIC OUTCOMES(PSOs)
|PSO 1||Design economically and technically sound analog and / or digital systems based on the principles of signal processing, VLSI and communication Engineering.|
|PSO 2||Integrate hardware – software, and apply programming practices to realize the solutions in electronics domain.|
Dr. vijaya c
Professor and Dean Academic Program
Dr. Shreedhar A Joshi
Professor & Head
Dr. Satish Bhairannawar
Professor & Dean III (Industry Institute Interface)
Prof. Savitri Raju
Associate Professor and COE
Dr. Hemalata Vasudev Bhujle
Dr. Kerur S. S.
Dr. Kalmeshwar N Hosur
Dr. S. V. Viraktamath
Associate Professor and PG Coordinator
Dr. Sharada C. Sajjan
Dr. Jayashree C Nidagundi
Dr. Siddalingesh S. Navalgund
Prof. Mala L Muddannavar
Prof. Vinayak P. Miskin
Asst. Professor, Placement Officer, Transport Incharge
Prof. Sumangala Bhavikatti
Dr. Sunil S Mathad
Prof. M. Vijay Kumar
Dr. Bairu K Saptalakar
Prof. S. S. Ravishankar
Prof. Kotresh Marali
Prof. Channakka Anand Kolur
Prof. Reshma Nadaf
Prof. Preeti Shivayya Bellerimath
Prof. Shrikanth Shirakol
Dr. Vyas R Murnal
Prof. Raghuram K M
UG – I – II Sem Syllabus ECE – AY 2023-24 |
UG – III – IV Sem Syllabus ECE – AY 2023-24
UG – V – VI Sem Syllabus ECE – AY 2023-24
UG – VII – VIII Sem Syllabus ECE – AY 2023-24
Recognition of Research Center
News Letter 2022-23
Space, Infrastructure & Facilities
|Laboratory Facility ECE Department|
Dr. Vijaya C (Professor and Dean Academic Program)
Prof. Dr. Vijaya C Received Research grants from AICTE RPS grants of Rs. 7 Lakh for DCT based Multimedia Applications, in 2011. Received VGST KFIST-L1 grants of Rs. 20 Lakh for Development of Advanced Communication Laboratory for Software Defined Radio, in 2019. Number of PhD guided: 04. Number of PhD guiding : 03. Contribution to NPTEL: Contributed study material in Higher Engineering Mathematics in NPTEL. Translated NPTEL course on Microprocessors and microcontrollers to Kannada Language as directed by NPTEL. Technical book: Coauthored a book on ‘Digital Signal Processing. Administrative responsibilities: Head of the Department in 2007 and 2010 for two years term each. Dean Academic Program in 2012-2015. Head of the Department since 2018.
Qualifications: B. E., M. Tech, Ph. D(R&D projects)
- Bottlenecks in Finite Impulse Response Filter Architectures on a Reconfigurable Platform Kunjan D Shinde, C Vijaya Recent Advances in Artificial Intelligence and Data Engineering, Volume, Year 2022, Pages 309-325.
- An Improved Nanoscale Quasi Balistic Double Gate (DG) MOSFET Model with drain bias dependency on critical channel length near low field source region by semi empirical approach Vijaya C., Vyas Murnal ICTACT Journal on Microelectronics, Volume 6, Year 2021, Pages 1020-1026
- 3D LEBP and 3D SPIHT based B Mode Echocardiogram Compression using variant transform Akshata S Konnur, C Vijaya Design Engineering, Volume, Year 2021, Pages 13861-13873
- Hand Gesture Recognition Using Semi Vectorial Multilevel Segmentation Murnal Vyas R Vijaya C. Nano Convergence, Volume 6, Year 2019
- A Quasi-Ballistic Drain current model with Positional Scattering Dependency applicable for Nanoscale DG MOSFETs,Vijaya C., Vyas Murnal, Proceedings of 2019 3rd IEEE International Conference on Electrical, Computer and Communication Technologies, ICECCT 2019, Volume, Year 2019
- Q-Factor Based Modified Adaptable Vector Quantization Techniques for DCT-Based Image Compression and DSP Implementation Mahendra M Dixit, C Vijaya, Innovations in Electronics and Communication Engineering, Volume, Year 2019, Pages 91-102
- Effects of hybrid SVD–DCT based image compression scheme using variable rank matrix and modified vector quantization Mahendra M Dixit, C Vijaya, Innovations in Computer Science and Engineering, Volume, Year 2019, Pages 513-522
- Image Quality Improvements Using Quantization Matrices of Standard Digital Cameras in DCT Based Compressor Mahendra M Dixit, C Vijaya, Journal of The Institution of Engineers (India): Series B, Volume 100, Year 2019, Pages 447-459
- Modelling and hardware implementation of quantization levels of digital cameras in DCT based image compression, Mahendra M Dixit, C Vijaya, Engineering Science and Technology, an International Journal, Volume 22, Year 2019, Pages 840-853
- Modified Automatic Digital Modulation Recognizer for Software Defined Radio, Sunil S Mathad, C Vijaya, Microelectronics, Electromagnetics and Telecommunications, Volume , Year 2019, Pages 433-442
- Brightness Mode Echocardiogram Image Compression using 3D LEBP and 3D SPIHT, Akshata S Konnur, C Vijaya, 2018 International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT), Volume , Year 2018, Pages 151-156.
- Q-Factor Based Modified Adaptable Vector Quantization Techniques for DCT-Based Image Compression, Mahendra M Dixit, C Vijaya, Innovations in Electronics and Communication Engineering: Proceedings of the 6th ICIECE 2017, Vol. 33, Year 2018, Pages 91
- Continuous Speech Recognition of Kannada language using triphone modeling Sharada C Sajjan, Vijaya C, 2016 International Conference on Wireless Communications, Signal Processing and Networking, (WiSPNET), Volume , Year 2016, Pages 451-455
- Comparison of DTW and HMM for Isolated Word Recognition Sharada C. Sajjan, Vijaya C. IEEE conference, Volume , Year 2012
- Algorithm for Distinguishing Modulation Techniques for SDR, Syed Salman, C Vijaya 2012 COMMUNE Conference on Advancements in Communication & Computing Systems, Year 2012
- DSP implementation of modified variable vector quantization based image compression using DCT and synthesis on FPGA, Mahendra M Dixit, C Vijaya, International Journal of Information Technology, Volume 11, Year 2011, Pages 203-212
- Computational analysis of adaptive singular value decomposition algorithm to 2D and 3D still image compression application, Mahendra M Dixit, C Vijaya, 2010 International Conference on Communication control and Computing Technologies, Volume , Year 2010, Pages 282-287
- Sliding discrete fractional transforms, Vijaya C, J.S. Bhat, Elsevier Signal Processing , Volume 88 , Year 2008, Pages 247–254
- Implementation of DFRFT for Signal Compression, Vijaya C, J.S. Bhat, Proc of 13th NCC 2007, IIT Kanpur, Volume , Year 2007, Pages 103-106
- Signal compression using discrete fractional Fourier transform and set partitioning in hierarchical tree, Vijaya C, J.S. Bhat, Elsevier Signal Processing , Volume 86, Year 2006, Pages 1976-1983
- Block Edge Detection in Discrete Fractional Fourier Transform Domain, Vijaya C, J.S. Bhat Proc of IEEE International Conference on on Signal and Image Processing at BVBCET Hubballi, year 2006, Pages 772-776
- Audio Codec based on DFRCT, Vijaya C, J.S. Bhat, Proc of NCC 2006, IIT New Delhi, Year 2006, Pages 190-193
- Perceptually Lossless Audio Codec based on Discrete Fractional Fourier Transform and SPIHT Vijaya C, J.S. Bhat, Proc of 13th International Conference on ADCOM-2005 at Amruta Vishwa Vidyapeetam, Coimbatore, Year 2005, Pages 434
- Digital Signal Processing, Vijaya C, Uday Kumar, Digital Signal Processing, Volume , Year 2004
- Signal Compression based on DFRFT and SPIHT, Vijaya C, J.S. Bhat, Proc of National Conference on ECCE 2004, TIET Patiala, Year 2004, Pages 187-190
Phone Number: 984 551 1315
- R & D Project: Establishment of Advanced Communication Laboratory to create teaching and research facility for Software Defined Radio
- Role: Principal Investigator
- Year 2019, Amount 20.00 Lakh
- Funding Agency: VGST
- R&d project Design Synthesis and implementation of Optimized Discrete Cosine Transform Based Signal Processing System for Multimedia Applications
- Role: Principal Investigator
- Year 2011, Amount 675000.00
- Funding Agency: AICTE
Dr. Shreedhar A Joshi (Professor and Head)
To contribute in the emerging field of Wireless Communication Technology and simultaneously work with Academic organizations to share the research experience for the next generation (3G & beyond) wireless LANs. RESEARCH INTERESTS : Wireless Communication, WSNs, 5G, 4G, LTE, MIMO and WSN, Networking and other wireless technologies.
Qualifications: BE in Electronics and Communication Engineering; M.Tech in Digital Electronics ( First RANK to VTU); PhD in Wireless networking technology
- Home automation system using wireless network Joshi, Shreedhar A and Poojari, Sunil and Chougale, Tushar and Shetty, Subrahmanya and Sandeep, MK Proceedings of the 2nd International Conference on Communication and Electronics Systems, ICCES 2017, Volume 2018-January, Year 2018, Pages 803-807
- Analysis and modeling of Generic Mac Protocols in Wireless Sensor Network Sheelavantar, Praneeta R and Joshi, Shreedhar A and Bidkar, Gopal A International Journal of Engineering and Technology(UAE), Volume 7, Year 2018, Pages 530-533
- Performance Comparison of Rectangular and Circular Micro-Strip Antenna at 2.4 GHz for Wireless Applications Using IE3D Gadag, Mahesh and Joshi, Shreedhar and Gadag, Nikit Lecture Notes in Networks and Systems, Volume 19, Year 2018, Pages 181-190
- Wireless controlled military combat robot system Joshi, Shreedhar A and Aravalli, Girishkumar and Vidyashree, AK and Ranade, Sampada and Badami, Shivalingappa S Proceedings of the 2nd International Conference on Communication and Electronics Systems, ICCES 2017, Volume 2018-January, Year 2018, Pages 712-715
- Iot Based Smart Energy Meter Dr. Shreedhar A Joshi, Srijay Kolvekar, Y. Rahul Raj and Shashank Singh International Journal of Trend in Scientific Research and Develpoment, Volume 6, Year 2017, Pages 89-91
- Analysis of RSSI and CLS based Localization Algorithms in Wireless Sensor Networks Joshi, Shreedhar A Bonfring International Journal of Research in Communication Engineering, Volume 6, Year 2016, Pages 16–19
- Data Hiding and Retrival Using Advanced Encryption and Decryption Algorithms Dr. Shreedhar A Joshi, Mamata Shetty International Journal of Engineering Research and Applications, Volume 4, Year 2014, Pages 17-20
- Studies on multiple input multiple output MIMO wireless systems with antenna selection and channel capacity Joshi, Shreedhara A Thesis, Volume , Year 2014, Pages
- FPGA implementation of CDMA trans-receiver Joshi, Shreedhar A and Sarangamath, Praveen B and Faras, Mohammed Irfan and Lakkannavar, Vishwanath 2012 International Conference on Education and e-Learning Innovations, ICEELI 2012, Volume , Year 2012
- Error propagation analysis of different detectors for V-BLAST MIMO channels Shreedhar A. Joshi ., T. S. Rukmini ., H. M. Mahesh ., Lecture Notes of the Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering, Volume 62 LNICST, Year 2012, Pages 120-125
- Dr. Mahesh H,” Analysis of V-BLAST Techniques for MIMO Wireless channels with different modulation techniques using Linear and Non Linear Detection” Joshi, Shreedhar A and TS, Dr Rukmini International Journal of Computer Science, Volume 1, Year 2011
- Receive Antenna Diversity and Subset Selection in MIMO Communication Systems Joshi, Shreedhar A and Rukmini, TS and Mahesh, HM ACEEE, Volume 2, Year 2011, Pages 130-134
- Space Time block coding for MIMO systems using Alamouti method with digital modulation techniques Joshi, Shreedhar A and Rukmini, TS and Mahesh, HM World Journal of Science and Technology, Volume 1, Year 2011, Pages 125–131
- Algorithm Design and Prototyping of Alamouti Encoder and Decoder with MIMO System Joshi, Shreedhar A and Rukmini, TS and Mahesh, HM Digital Signal Processing, Volume 3, Year 2011, Pages 87–92
- Error rate analysis of the V-BLAST MIMO channels using interference cancellation detectors Shreedhar A. Joshi ., T. S. Rukmini ., H. M. Mahesh ., 2011 – International Conference on Signal Processing, Communication, Computing and Networking Technologies, ICSCCN-2011, Volume , Year 2011, Pages 614-618
- Modeling and capacity analysis of correlated MIMO channels Dr. Shreedhar A Joshi International Journal of Engineering Science and Technology , Volume 2, Year 2010, Pages 5419-5423
- Performance analysis of MIMO technology using V-BLAST technique for different linear detectors in a slow fading channel Shreedhar. A. Joshi ., T S Rukmini ., H M Mahesh ., 2010 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2010, Volume , Year 2010, Pages 453-456
- System performance analysis of MIMO channel capacity with channel state approaches Shreedhar A Joshi ., T S Rukmini ., H M Mahesh ., 2010 IEEE International Conference on Communication Control and Computing Technologies, ICCCCT 2010, Volume , Year 2010, Pages 71-76
Phone Number: 871 080 9870, 808 349 0120
- SCHEME FOR PROMOTING INTRESTS, CREATIVITY AND ETHICS AMONG STUDENTS (SPICES); Funding Agency : AICTE; Role: COORDINATOR; Year 2021-22, Amount Rs.100000 /- ; STILL IN PROGRESS;
- DIGITAL CLASS ROOM ; Funding Agency : NPIU; MHRD ; TEQIP 1.2 ; Role: COORDINATOR Year 2019, Amount Rs. 590304/- ; Completed in January 2020.
Dr. Satish Bhairannawar (Professor & Dean III – Industry Institute Interface)
Dr. Satish S Bhairannawar is the Dean of Industry Institute Interface (III), and Professor of Electronics & Communication Engineering, SDMCET, Dharwad and also he is a visiting faculty for the subject VLSI Design, IIIT, Dharwad. He was associated with Prof. L. M Patnaik, SERC, IISc for research activities in 2005. He is currently in process of registering his Post-Doctoral Fellowship research at University of Manitoba, Canada on “AI based Assistive Device for treatment of Cerebral Palsy Children”. He has served in Department of Electronics and Communication, DSCE, Bangalore before joining to SDMCET. He has been involved in research activities funded by reputed state and central Govt. Organizations and has completed sponsored research projects from DST and K-BITS. Currently, he is in to AI based precision agriculture project funded with Rs.30 Lacs by VGST KFIST L2, Government of Karnataka. He has filed and published one patent titled “1D-DWT and 2D-DWT Architecture with Enhanced Speed”. He has also contributed to Book Chapter titled: “Efficient medical Image Enhancement using HSV & CLAHE Technique”, Soft Computing Medical Image Enhancement – Elsevier Publication. He has over 30 research publications in SCIE, ECSI & SCOPUS indexed International Journals and Conference Proceedings and also served as reviewer including IEEE, Springer and Elsevier. He also received Best paper award in IEEE international conference organized by VIT, Vellore for the paper titled “Efficient image enhancement using modified adaptive histogram equalization”. His papers have over 132 citations with a h-index of 7 and i10-index of 5. He has conducted many Faculty Development and Student Training program in area of Image Processing using MAT LAB, RTL Design using HDL, Advanced VLSI Design and many more in reputed engineering colleges like PES University, KLE university, Dr. AIT, Bangalore etc. He is expert reviewer for Medical Device Hackathon (eMEDHA) organized every year by BETIC, IIT Bombay also he is startup advisor to University of Agricultural Science, Dharwad. He is technical consultant to few Startups in INDIA. He as a chairperson CEIR Startups, SDMCET, Dharwad is responsible to build an incubation eco-system for 6 startups in campus by nurturing them with necessary fund up to Rs.1.8 Crores from reputed government organizations. He also a founder of Crofting Technologies which is mainly in to developing technology based products in the field of medicine and agriculture. Crofting Technologies has been awarded as the winner of ELEVATE-2020 for funding 25 Lacs by department of ITBT S&T Govt of Karnataka for the product titled “Foot track-1.0: Walking Pressure analyser using treadmill for physically disabled people, with the aid of exoskeleton” He has been recognized with young researcher award in the year 2017 by InSc (An ISO 9001:2015 Certified Institute by International Accurate Certification, Accredited by UASI) and also conferred with the title Senior Member, IEEE for personal and professional commitment to the advancement of technology by IEEE, USA.
Qualifications: B. E., M. Tech, Ph. D
Phone Number: 998 600 8419
- Outstanding Faculty Advisor Award for Small Student CAS Branch Chapter by IEEE CAS Bangalore, 2020.
- Young Researcher Award by InSc in 2017 (An ISO 9001:2015 Certified Institute by International Accurate Certification, Accredited by UASI)
- Received Best paper award in IEEE international conference organized by VIT, Vellore for the paper titled “Efficient image enhancement using modified adaptive histogram equalization, 2017
Prof. Savitri Raju (Associate Professor)
Working in the Department of Electronics and Communication Engineering since 1995.
Qualifications: B. E., M. E.
Phone Number: 948 025 4450
Dr. Hemalata Vasudev Bhujle(Associate Professor)
Dr. Hemalata Bhujle received her B.E. degree from Karnataka University, Dharwad in 1997, M.E. degree from the University of Pune in 2004 and PhD from the Electrical Engineering Department of IIT Bombay in 2013. She is currently serving as an Associate Professor in the Department of Electronics & Communication Engineering, SDMCET, Dharwad. She has published many papers in reputed journals /conferences. She is a reviewer for IEEE letters, MRI journal (Elsevier), Journal of electronic imaging. She is a recipient of young scientist award from VGST, Govt. of Karnataka. Her research interests include signal and image processing.
Qualifications: Ph. D
- Hemalata Bhujle and Subhasis Chaudhuri. “Novel speed-up strategies for NLM denoising with patch and edge patch based dictionaries” IEEE Transactions on Image processing, (2014) 23:356-365.
- Hemalata Bhujle and Subhasis Chaudhuri. “Laplacian Based MR image Denoising with Rician Noise” Magnetic Resonance Imaging (Elsevier Journal), (2013) 31: 1599:610.
Phone Number: 998 680 7954
- KFIST-L1 research grant from VGST, Bangalore
Dr. KERUR S S (Associate Professor)
VLSI,REAL EMBEDDED SYSTEMS
Qualifications: Ph. D
Phone Number: 821 788 1146
Dr. Kalmeshwar N Hosur (Associate Professor)
Kalmeshwar N Hosur received Bachelor of Engineering in Electronics and Communication Engineering from Karnataka University Dharwad, Master of Technology in VLSI Design and Embedded Systems from Visvesvaraya Technological University, Belgaum and Ph.D in the field of VLSI from Visvesvaraya Technological University, Belgaum. Since 2000, he is serving as faculty in the Dept. of Electronics and Communication Engineering, S. D. M. College of Engineering and Technology, Dharwad, Karnataka. His main research interests include Analog Electronics, Analog and Mixed Mode VLSI Design and Embedded System Design. Kalmeshwar N Hosur is currently the life member of Institution of Electronics and Telecommunication Engineers (IETE), Indian Society for Technical education (ISTE) and Institution of Engineers India (IE-I).
Qualifications: Ph. D
- Published paper entitled “Design, Implementation and Macro-Modeling of 1.2V, 10-Bit SAR ADC using VLSI Technique” in an International Journal of Computational Intelligence and Telecommunication System, Vol.1.N0.1, Jan-June 2010.
- Published paper entitled “Design, Implementation and Analysis of Flash ADC Architecture with Differential amplifier as comparator using Custom Design Approach” in an International Journal of Electronics Signals and Systems (IJESS) ISSN: 2231- 5969, Vol-1 Iss-3, 2012.
- Published paper entitled “Analysis and Experimental Results of Interior DAC of SAR ADC using Cadence” in an IOSR Journal of VLSI and Signal Processing (IOSR-JVSP), Volume 4, Issue 4, Ver. II (Jul-Aug. 2014), PP 35-39, e-ISSN: 2319 – 4200, p-ISSN No. : 2319 – 4197
- Published paper entitled “DESIGN AND IMPLEMENTATION OF 10 BIT 2MS/s SPLIT SAR ADC USING 0.18um CMOS TECHNOLOGY”, in an International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.3, June 2015, DOI : 10.5121/vlsic.2015.6302.
- Published paper entitled “Design and simulation of 3 bit Flash ADC using Quantum Voltage Comparator with 0.3um CMOS Technology in static electric 9.05”, in an International Journal of Advanced Research Trends in Engineering and Technology (IJARTET) Vol. II, Special Issue XXVII, June 2015 in association with DAYANANDA SAGAR COLLEGE OF ENGINEERING, KUMARASWAMY LAYOUT, BENGALURU- 560 078 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING ORGANIZES DRDO SPONSORED NATIONAL CONFERENCE ON “EMERGING TRENDS IN VLSI, EMBEDDED SYSTEM, NANO ELECTRONICS AND TELECOMMUNICATION SYSTEM” DSCE NCEVENT’15 JUNE 16 & 17,2015.
- Published paper entitled “Design and Simulation of Low Power Successive Approximation Register for A/D Converters using 0.18um CMOS Technology”, in an International Journal of Engineering and Technology (IJET), e-ISSN : 0975-4024, p-ISSN : 2319-8613, Vol 8 No 2 Apr-May 2016.
- Published paper entitled “DESIGN OF A LINEAR AND WIDE RANGE CURRENT STARVED VOLTAGE CONTROLLED OSCILLATOR FOR PLL” in an International Journal on Cybernetics & Informatics (IJCI) Vol.2, No.1, February 2013, DOI : 10.5121/ijci.2013.2104.
- Published paper entitled “Neural Network Based Implementation of Corner Detection for Biomedical Application in Computer Vision”, in an International Journal of Indian Journal of Public Health Research & Development, Volume 11, March 03, March 2020, ISSN-o976-0245 (print).ISSN-0976-5506 (Electronic).
- Published paper entitled “Automatic Grading of Diabetic Retinopathy through Machine Learning” in an International Journal of Innovative Technology and Exploring Engineering (IJITEE) ISSN: 2278-3075, Volume-9 Issue-9, July 2020, Retrieval Number: I7148079920/2020©BEIESP DOI: 10.35940/ijitee.I7148.079920, Published By: Blue Eyes Intelligence Engineering and Sciences Publication.
- Published paper entitled “Design and Analysis of 10-bit, 2 MS/s SAR ADC Using Nonredundant SAR and Split DAC”, In: Nath V., Mandal J. (eds) Proceeding of the Second International Conference on Microelectronics, Computing & Communication Systems (MCCS 2017). Lecture Notes in Electrical Engineering, vol 476. Springer, Singapore. https://doi.org/10.1007/978-981-10-8234-4_65.
Phone Number: 0836-248273
- R & D Project: Instituting an intelligent Innovation Lab setup for precision agriculture services. Role: Co-Principal Investigator, Year 2020, Amount 30.00 Lakh. Funding Agency: VGST, Government of Karnataka.
KSCST Sponsored Projects:
- Title: Eye Monitored Wheel Chair, Year: 2017-18
- Title: Network Coprocessor Implementation on FPGA, Year : 2009-10
- Served as guest faculty to Government Engineering College, Haveri.
Dr. S. V. Viraktamath (Associate Professor and PG Coordinator)
Dr. S. V. Viraktamath has undergone 12 years of technical education, received Gold medal from VTU. He has served Tontadarya College of Engineering and Anjuman college of Engineering as a faculty in the Dept. of E&CE. He is serving SDMCET since 2004. He has received a best teacher award from SDMCET. He has served as a guest faculty to KUD, Govt. Engg. College Haveri. He has organised many activities for the students. He is serving as PG coordinator, Coordinator of Bosch Rexroth Centre of Excellence, SDMCET also BOS member of EC Dept. and academic council member of SDMCET. He has more than 24 years of teaching experience. He is the life member of ISTE, IETE and IE.
Qualifications: Ph.D (Undergone 12 yers of technical education JTS, DTE, BE, M.Tech)
- Performance Analysis of Convolutional CODEC for Distributed and Burst Errors” is published in the Coimbatore Institute of Information Technology International Journal Digital signal processing Vol 3, N0 2, March 2011 (IF 0.126) (CiiT International Journal) DOI: DSP032011008. Print: ISSN 0974 – 9691 & Online: ISSN 0974 – 9586. ISBN: 978-1-4244-5966-7.
- High Throughput Lossless Data Compression Algorithm”, International Journal on Advanced Computer Engineering and Communication Technology Vol-1 Issue:1 :ISSN 2278 – 5140 http://www.irdindia.in/journal_ijacect/pdf/vol1_iss1/10.pdf
- “Impact of Quantization Matrix on the Performance of JPEG”, is published in International Journal of Future Generation Communication and Networking, Vol. 4, No. 3, September, 2011, page Nos:107-118, ISSN 2233-7857. https://www.earticle.net/Article/A153577 http://article.nadiapub.com/IJFGCN/vol4_no3/10.pdf
- “Face Detection and Tracking using OpenCV”, The SIJ Transactions on Computer Networks & Communication Engineering (CNCE) Print ISSN: 2321 – 239X | Online ISSN: 2321 – 2403. http://www.thesij.com/papers/CNCE/2013/July-August/CNCE-0103540102.pdf
- Dr. S. V. Viraktamath, Prof.shamstabriz M. Asadullah, “Classification of Twitter Spam Based on profile and message model using SVM” is published in IRJET Journal Volume 4 Issue 5 May 2017. https://www.irjet.net/archives/V4/i5/IRJET-V4I5718.pdf
- “A Survey on Retinal Blood Vessel Extraction and Segmentation Techniques” © 2019 JETIR February 2019, Volume 6, Issue 2 www.jetir.org (ISSN-2349-5162) JETIRAB06015 Journal of Emerging Technologies and Innovative Research (JETIR) www.jetir.org Page No 69-72. http://www.jetir.org/papers/JETIRAB06015.pdf
- “Lane Departure and Collision Controlling using Image Processing” International Journal of Engineering and Advanced Technology (IJEAT) ISSN: 2249 – 8958, Volume-8 Issue-6, August 2019. Published By: Blue Eyes Intelligence Engineering & Sciences Publication. Retrieval Number F8498088619/2019©BEIESP DOI: 10.35940/ijeat.F8498.088619. page no 1267 – 1271. IJEAT is a SCOPUS Journal. http://doi.org/10.35940/ijeat.F8498.088619, https://www.ijeat.org/wp-content/uploads/papers/v8i6/F8498088619.pdf
- Optimized PN Sequence Generation using Elliptic Curve Cryptography and UWD, International Journal of Recent Technology and Engineering (IJRTE) ISSN: 2277-3878, Volume-8, Issue-2S11, September 2019. Retrieval Number: B12050982S1119/2019©BEIESP DOI: 10.35940/ijrte. Published By: Blue Eyes Intelligence Engineering & Sciences Publication Page 2085-2090. http://doi.org/10.35940/ijrte.B1205.0982S1119
- The publication information is available at: http://svvpapers.blogspot.com https://tinyurl.com/svvpapers
Paper Presentation in Conferences/ Full paper in Conference Proceedings (Few):
- Error Control Mechanism Using CODEC” has been published in proceedings of “International Conference on Communication Software and Networks 2009” (ICCSN 2009), February 27 – 28, 2009. Macau, China. doi.org/10.1109/ICCSN.2009.142. https://ieeexplore.ieee.org/document/5076912/
- “Performance analysis of JPEG algorithm”, “International Conference on Signal Processing, Communication Computing and Networking Technologies” July 21-22/ 2011, IEEE Catalog Number CFP1160N-C-CDR https://ieeexplore.ieee.org/document/6024627/
- “Power Saving Mechanism for street lights using wireless communication”, “International Conference on Signal Processing, Communication Computing and Networking Technologies” July 21-22/ 2011, Noorul IslamCentre For Higher Education, Kumaracoil, Thuckalay, Kanyakumari district, Tamil Nadu. ISBN Number: 978-1-61284-652-1, IEEE Catalog Number CFP1160N-C-CDR, https://ieeexplore.ieee.org/document/6024560
- “Blood Vessels extraction of retinal image using morphological operations”, International Conference on Innovative Research in Computing Applications (ICIRCA 2018), organized by RVS College of Engineering and Technology, during July 11-12, 2018 at Coimbatore, Tamil Nadu, India. ISBN:978-1-5386-2456-2,doi.org/10.1109/ICIRCA.2018.8597352, link: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8597352
- Few more paper details is available at IEExplore: https://ieeexplore.ieee.org/search/searchresult.jsp?newsearch=true&queryText=viraktamath
- “BER Performance Comparison between HOVA, SOVA and MAP Turbo Decoders in AWGN Channel”, Third international Conference on Emerging Research in Computing, Information, Communication and Applications-ERCICA 2015. ERCICA 2015, Volume3, eBookISBN: 978-981-10-0287-8, DOI:10.1007/978-981-10-0287-8, Publisher Springer-Verlog Singapore. https://link.springer.com/book/10.1007/978-981-10-0287-8?page=2#toc
- “Implementation of Automated Bottle Filling System using PLC”, Book Series: Lecture Notes in Networks and Systems, Inventive Communication and Computational Technologies pp 33-41, Print ISBN: 978-981-15-0145-6, Electronic ISBN: 978-981-15-0146-3, Publisher: Springer Singapore, Conference paper First Online: 30 January 2020. Part of the Lecture Notes in Networks and Systems book series (LNNS, volume 89). https://link.springer.com/chapter/10.1007/978-981-15-0146-3_4 https://www.springerprofessional.de/en/implementation-of-automated-bottle-filling-system-using-plc/17635130
- “Performance comparison of Machine Learning Models for Detection of Fake News”, 3rd International Conference on Intelligent Computing, Information and Control Systems ICICCS 2021 | 02-03 July, 2021, published in Springer – Advances in Intelligent Systems and Computing Series ISSN: 2194-5357, http://iciccs.com/2021/ https://link.springer.com/bookseries/11156
- “Color Image Compression using YCbCr and CIELAB Color Spaces”, Proceedings of ‘Second International Conference on Emerging Research in Computing, Information, Communication and Applications’, ERCICA-2014, ISBN 9789351072621, © Elsevier Publications 2014, Pages 813-818. https://www.nmit.ac.in/ercica/pdf/ERCICA-2014-Volume%20I.pdf
- “Performance Simulation of Convolutional CODEC for image transmission in AWGN Channel”, Proceedings of ‘Second International Conference on Emerging Research in Computing, Information, Communication and Applications’, ERCICA-2014, ISBN 9789351072638, © Elsevier Publications 2014, Pages 538-542. https://www.nmit.ac.in/ercica/pdf/ERCICA-2014-volume-III-Lowres-pdfs-24thSep14.pdf
Phone Number: 0836-2328281 (O)
- Received Gold medal from VTU for securing First rank to the VTU.
- Served as Adviser (Sports) of SDMCET.
- Served as Chairman, Vice Chairman and secretary of IETE Dharwad sub centre.
- Serving as PG coordinator of SDMCET.
- Serving as Coordinator of Bosch Rexroth Centre Of Excellence, SDMCET.
- Received Best teacher award from SDMCET during 2010.
- Published/ Presented papers with more than 90 students.
- Obtained the Certificate of Appreciation from NPTEL for translating the course on “Electromagnetic Theory” into Kannada language.
- Two projects under my guidance received KSCST-sponsorship.
- Training programs conducted on: PCB Design, Microprocessor 8085 programming.
Dr. Sharada C. Sajjan (Associate Professor)
Interested to handle subjects in the field of signal processing and communication.
Qualifications: M.E., Ph.D
- Sharada C. Sajjan, Vijaya C, “Time-Frequency Analysis of Kannada Phonetics”, IJARSCT, 2021
- Sharada C. Sajjan, Vijaya C, “Kannada Speech Recognition using Decision Tree Based Clustering”, Springer Nature Singapore, 2018.
- Sharada C. Sajjan, Vijaya C, “Continuous Speech Recognition of Kannada Language using Triphone Modeling”, IEEE Explore, 2016.
- Sharada C. Sajjan, Vijaya C, “Speech Recognition Using Monophone and Triphone Based Continuous Density Hidden Markov Models”, IJRSI, 2015
- Sharada C. Sajjan, Vijaya C, “Comparison of DTW and HMM for Isolated Word Recognition”, IEEE Explore, 2012.
- Sharada C. Sajjan, Vijaya C, “Speech Recognition using Hidden Markov Models”, WJST, 2011.
- Vijayalaxmi V K, Sharada C. Sajjan, “Fire Detection using YCbCr Color Model”, IJSRSET, ISSN:2394-4099, 2016.
- Trupti Thite, Sharada C. Sajjan, “Palmprint Texture Analysis using 1D Log-Gabor Filter”, IJRTE, ISSN:2277-3878, 2014.
Phone Number: 944 950 0828
- Received funding from IEI-VTU of amount 50,000.00 for the project proposal in 2012.
- Working as PG coordinator and IQAC coordinator of the department
Dr. Jayashree C Nidagundi (Associate Professor)
Working as Associate Professor in the dept. of E&CE, SDMCET Dharwad since from 2004. Earlier I have worked as Lecturer in the Dept. of E&CE, BVBCET, Hubli for two years. Total teaching experience of 20 years. Area of Interest is VLSI Design & Embedded Systems, IoT, Error Control Coding. Guided several UG and PG projects.
Qualifications: B. E., M. Tech, Ph. D
- Prakash Narchi, Siddalingesh S Kerur, Jayashree C Nidagundi, Harish M Kittur and Girish V A. Implementation of Vedic Multiplier for Digital Signal Processing. International Journal of Computer Applications (IJCA) 2011; 16:1-6
- Kunjan Shinde. Jayashree C. Nidagundi, Dr. Siddarama R. Patil. FPGA. Implementation of Fast Error Correction and Detection for Memories. Journal of Innovations in Engineering and Technology (IJIET) 2013; 1: 70-78 ISSN: 2319-1058
- Jayashree Nidagundi, Harish Desai, Shruti A., Gopal Manik. Design and Implementation of Low Power Phase Frequency Detector (PFD) for PLL. International Journal of Scientific Engineering and Technology(IJSET) 2013; 2: 160-163.ISSN : 2277-1581
- Jayashree C. Nidagundi, Dr. Siddarama R. Patil. Performance Comparison of Binary LDPC Decoders and FPGA Implementation of Encoder Bonfring International Journal of Research in Communication Engineering 2016; 6:65-70 DOI: 10.9756/BIJRCE.8203
- Jayashree C Nidagundi. IMPROVED HIGH-SPEED LDPC ENCODER ARCHITECTURE FOR IEE 802.3an STANDARD” International Journal of Creative Research Thoughts-IJCRT 2020; 7:4821-4830. ISSN: 2320-2882
- Jayashree C Nidagundi. EFFICIENT DESIGN OF LVDS TRANSMITTER IN COMPLIANCE WITH IEEE STANDARD 1596.3-1996. Journal on Microelectronics(ICTACT) 2020; 3:987-990 ISSN: 2395-1680 (ONLINE) DOI: 10.21917/ijme.2020.0171
- Prof. Jayashree C. Nidagundi, Prof. Dr. Siddarama.R. Patil. Flexible Hardware Architecture for LDPC Encoder. International Conference on Green Engineering and Technology (IC-GET) 2016;INSPEC Accession Number: 16864772 DOI: 10.1109/GET.2016.7916782
- Prof. Jayashree C. Nidagundi. Prof. Dr. Siddarama.R. Patil. High Throughput Structured LDPC Layered Decoder. International Conference on Wireless Communications, Signal Processing and Networking (IEEE,WiSPNET) 2017;INSPEC Accession Number: 17598678 DOI: 10.1109/WiSPNET.2017.8300023
- Jayashree C Nidagundi. Design of I/O Interface for DDR2 SDRAM Transmitter using gpdk 180nm Technology. 10th International Advanced Computing Conference (IACC) 2020; Book chapter:Springer Singapore
Phone Number: 924 214 9952
Dr. Siddalingesh S. Navalgund (Assistant Professor)
Siddalingesh S. Navalgund received Bachelor of Engineering in Electronics and Communication Engineering from Karnataka University Dharwad and Master of Technology in Microelectronics and Control Systems from Visvesvaraya Technological University, Belgaum. After spending two years in the industry, he joined as a faculty in N. M. A. M. in Institute of Technology, Nitte, Karnataka. Since 2005, he is serving as faculty in the Dept. of Electronics and Communication Engineering, S. D. M. College of Engineering and Technology, Dharwad, Karnataka. His main research interests include Analog design, VLSI design, embedded & fuzzy systems and digital signal processing. Prof. Navalgund is currently the life member of Institution of Electronics and Telecommunication Engineers (IETE), Indian Society for Technical education (ISTE) and Institution of Engineers India (IE-I).
Qualifications: B. E., M. Tech, Ph. D
- Mamatha. L. Japate, S. S. Navalgund, “Chaos based Encryption of Image for Secure Communication”, International Journal of Recent Technology and Engineering (IJRTE) ISSN: 2277-3878, Volume-9 Issue-1, May 2020, Retrieval Number: A2615059120 / 2020 ©BEIESP DOI:10.35940/ijrte.A2615.059120, pp 1694 – 1699.
- Sangeeta. M. Gangannavar, S. S. Navalgund and Satish S. Bhairannawar, “A Reconfigurable Architecture for Object Detection using Adaptive Threshold”, International Journal of Advanced Computer Research (IJACR), Volume – 8, Issue – 38, September – 2018, ISSN 2277-7970, pp. 257 – 267. DOI:10.19101/IJACR.2018.838006.
- S. S. Navalgund, S. S. Kerur, Kotresh Marali, “IoT based Intelligent Autonomous Vehicle on Multicore Processors”, International Journal of Advance Research and Innovation (ISSN 2347-3258), pp 1-7, 2017.
- Siddalingesh S.Navalgund, Dr. Mrityunjaya V. Latte, “Manual Placement and Routing in Multipliers with Trivial Operands”, International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, Vol. 5, Issue 1, January 2016, ISSN (Print) : 2320 – 3765 ISSN (Online): 2278 – 8875, pp 286-295, DOI:10.15662/IJAREEIE.2015.0501051.
- K.U.Prateek, B. Dinesh Ballullaya, R. L. Chakrasali, S.S.Navalgund, Medium Access Control CSMA/CA Binary Countdown Protocol for SCADA Application, EJERS, European Journal of Engineering Research and Science Vol. 1, No. 4, October 2016, pp.15-19.
- Siddalingesh S.Navalgund, Bairu K. Saptalkar, Dr. Mrityunjaya V. Latte, “A Novel Design Procedure for Increased Configurable Logic Block Capacity in FPGAs”, International Journal of Advance Research In Science And Engineering http://www.ijarse.com IJARSE, Vol. No.3, Issue No.10, October 2014, pp 268-276, ISSN-2319-8354(E)
- Ashwini S. Karne and S. S. Navalgund, “Implementation of image thinning algorithm using Verilog and MATLAB”, International Journal of Current Engineering and Technology, ISSN 2277 – 4106 ©2013 INPRESSCO. All Rights Reserved Available at http://inpressco.com/category/ijcet, pp 333-337.
- Kumara Swamy H. L., Kotresh E. Marali, Siddalingesh S. Navalgund , Novel Techniques for Circumventing the Glitch effects on Digital Circuits for Low-Power VLSI Design, International Journal of Engineering Research & Technology (IJERT) Vol. 2, Issue 3, March – 2013 ISSN: 2278-0181, pp.1-5.
- Daneshwari I. Hatti, Siddalingesh S. Navalgund and Vijaya C., Neural Network Based DCT Computation, International Journal on Advanced Computer Engineering and Communication Technology Vol-1 Issue:1 :ISSN 2278 – 5140, pp. 81-86.
- Daneshwari I. Hatti, Siddalingesh S. Navalgund, Design of Fuzzy Logic Controller for Industrial Motor Control Application, International Journal of Research and Reviews in Engineering Sciences–IJRRES, Vol 01, Issue 01; April 2012, pp. 37-44.
- Prakash Tonse, Shubhalakshmi Shetty, Shruti S.R., Siddalingesh S. Navalgund, “Design and Implementation of an Embedded System for Fuzzy Logic based Traffic Light Controller”, Special Issue of International Journal of Computer Applications (0975 – 8887) International Conference on Electronic Design and Signal Processing (ICEDSP) 2012, pp. 16-20.
- Vikram Banerjee, Prakash Tonse , Shruti S.R., Shubhalakshmi Shetty, Siddalingesh S. Navalgund, Kotresh E. Marali, “Design Space Exploration Of Mamdani And Sugeno Inference Systems For Fuzzy Logic Based Illumination Controller”. International Journal of VLSI and Embedded Systems-IJVES, Vol 03, Issue 01; January-April 2012, ISSN: 2249 – 6556 (IJVES-Y12-TJ-SA-C040), pp: 97-101.
- S.V.Viraktamath, Dr. G.V.Attimarad, S.S. Navalgund “Convolutional CODEC using SOVA for Image applications” is published in International Journal of Machine Intelligence and Applications- Vol. 2 no. 1 Jan-June 2011. Published By: International Sciences Press ISSN: 0976-6227 Frequency: Bi-Annual.
- S.S.Navalgund, Mahendra M. Dixit, S. S. Kerur, Anil V. Nandi, Dr. Mrityunjaya V. Latte, “Design and Implementation of an Optimized Single-Precision floating Point Multiplier on FPGA”, International Journal on Information and Communication Technologies, vol. 2, No. 1-2, January-June 2009, pp. 149-153.
Phone Number: 0836-2447465
- Obtained the Certificate of Appreciation from NPTEL for translating the course on “Electrical Distribution System Analysis” into Kannada language, November 2020.
- Editor of ET-Talk, the monthly news bulletin of the IE(I)-Dharwad Local Center.
- KSCST-sponsored student project titled “Embedded Navigation System for aiding People with Alzheimer’s Disease” during the academic year 2011-12.
- KSCST-sponsored student project titled “Gesture-Based human Machine Interface using Accelerometers” during the academic year 2010-11.
- Awarded National Merit Scholarship during engineering studies.
- Training programs conducted on:
- Scientific Computing using Python
- Model-based design using Simulink
- Pointers in C
- Object-oriented Programming using C++
- Introduction to MATLAB
Prof. Mala L Muddannavar (Assistant Professor)
Complited BE in Electronics and communication Engineering.ME in power electronics.Working at SDMCET since 2005.Area of Intrest Digital design Embeded systems, Cryptography.Guided 30 U.G. and 05 P.G. students .Life member of ISTE and IETE.
Qualifications: ME (PE)
- Secured Biometric Authentication of Iris Image using Visual Cryptography. Authors- Shafiqua Noorain, Mala L Muddannavar. International Journal of Engineering and Advanced Technology (IJEAT), ISSN: 2249-8958, Volume-9 Issue-6, August 2020
Phone Number: 944 964 1101
- NPTEL courses completed
Prof. Vinayak P. Miskin (Asst. Professor, Placement Officer, Transport Incharge)
Qualifications: M. Tech
Phone Number: 0836-2447465
Prof. Sumangala Bhavikatti (Assistant Professor)
Completed B.E from R.E.C Hulkoti and M.Tech from B.V.B CET Hubli. I am persuing PhD in the field of Image processing.Member of IE ,IEEE and IETE.
Qualifications: M. Tech
- Presented paper “ Neural network s based handwritten character recognition system” in ICCSME.
Phone Number: 948 101 1691
- Given a talk on image processing in IE.
Dr. Sunil S Mathad (Assistant Professor)
Working as Asst. Professor in E &CE Dept. of S.D.M.C.E.T. Dharwad since August 2009. In due course have handled subjects like ARM Processor, Computer Architecture, Real Time Operating Systems, High Speed System Design, VLSI Design. Service has rendered the exposure to the laboratories such as LPC2148 (ARM7TDMI) based board, LPC1763 (CORTEX M3) based boards, usage of RTX kernel. Keil Microcontroller Design Kit (MDK) on which the debug and development of ARM based Devices were carried out. MATLAB 14.1 along with Simulink (Signal Processing and Communication Toolbox) LabVIEW 14 and LabVIEW Communication System Design Suite along with USRP2920. Cadence tools (Virtuoso, Encounter, Diva, Dracula) for VLSI XILINX FPGAs namely Spartan-II, Spartan-III, Spartan-VI and Virtex V XILINX ISE 14.7 Environment. Code blocks and gcc toolchains PLC CML20 and Indralogic and Indraworks.
Qualifications: B.E. in Electronics and Communication Engineering ; M.Tech [VLSI Design and Embedded Systems]; Ph. D. [ Electrical and Electronics Engineering Sciences]
- Mathad S.S., Vijaya C. (2019) Modified Automatic Digital Modulation Recognizer for Software Defined Radio. In: Panda G., Satapathy S., Biswal B., Bansal R. (eds) Microelectronics, Electromagnetics and Telecommunications. Lecture Notes in Electrical Engineering, vol 521. Springer, Singapore. https://doi.org/10.1007/978-981-13-1906-8_45
- Mathad, S.S., Vijaya, C. Revised architecture for automatic modulation recognition. Int. j. inf. tecnol. 12, 605–610 (2020). https://doi.org/10.1007/s41870-019-00376-w
Phone Number: 988 050 2110
Prof. M. Vijay Kumar (Assistant Professor)
I am currently working as Assistant Professor in Electronics and Communication Engineering department, SDM College of Engineering and Technology, Dharwad. I have 15 years of teaching experience. Basically i teach Control System, Engineering Electromagnetics, Basic Electronics, Digital Circuit Design, Microcontrollers etc… I have guided several UG and PG Projects.
Qualifications: B.E. (E&CE), M.Tech. (Digital Electronics)
- Dr. S.S.Navalgund, Dr. S.S.Kerur, M. Vijay Kumar, Innovations in Technical Education: “A Case study at SDMCET”, Proceedings of the 48th ISTE National Annual Faculty Convention-2019 on Technical Education for Smart Society, Organized by VTU Belagavi 19,20 March 2019.
- Sudha D. Koppad and M. Vijay Kumar, “Image Segmentation using Gradient Descent Method”, International Journal Of Recent Advances in Engineering & Technology (IJRAET), June 2014, ISSN (Online): 2347-2812.
- Prof. Vivek Pattanshetti , Prof. M. Vijay Kumar, “Performance Evaluation of Fuzzy based Water bath System with Variation in Number of Linguistic Variables and Membership Function Range”, International Journal of Advance Research in Engineering, Science & Technology e-ISSN: 2393-9877, p-ISSN: 2394-2444 Volume 3, Issue 5, May-2016. Impact Factor (SJIF): 3.632
- Supriya C Banakar , M.Vijay Kumar, “Satellite Image Resolution Enhancement Using DWT”, Proceedings of International Conference on Computer Science and Engineering (ICCSE 2012), 28th June, 2012, Pune, India. ISBN: 978-93-81693-93-3
Phone Number: 948 072 4799
- Completed project “Development of Electronics Based Models for Science Subject for Primary / High School” ,Under Unnat Bharat Abhiyan (UBA) , a flagship program of Ministry of Human Resource Development, Govt. ofIndia. https://www.youtube.com/playlist?list=PLfug9k7EEbSEL2HNeVdbJAolie2DYuovT
- Radio Talk on the Topic “ಡಿಜಿಟಲ್ ಇಂಡಿಯಾ ಒಂದು ಪರಿಕಲ್ಪನೆ ಮತ್ತು ವಾಸ್ತವ” as part of SDM Radio Engineeer swalpa kelri on 28/09/2021.
- Technical article on “Digital India Making our Lives Easy” for Institution of Engineers magazine on 25/09/2021.
- Programmes conducted for students i.) Career Guidance Tips in Programming ii.) Exploring Pointers in C iii.) Training on Refresher Course as a part of training for campus placements; on July 27,2020, July 28-31, 2020, Aug 10-12, 16, 2019 respectively.
- Conducted Refresher course on “Digital Circuit Design” for students 23rd August 2015.
Dr. Bairu K Saptalakar (Assistant Professor)
Working Assistant Professor Since from 2010 in this institution.
Qualifications: M. Tech
- Effective reflection removal system for cognitive based convolutional neural networkss
- FPGA-based reflection image removal using cognitive neural network
Phone Number: 988 005 7335
Prof. S. S. Ravishankar (Assistant Professor)
I have been working in SDMCET for more than 11 years. I have handled the subjects Antenna & Wave Propagation, Management Entrepreneurship & IPR and Microcontrollers.
Qualifications: M. Tech
Phone Number: 988 051 2162
Prof. Kotresh Marali (Assistant Professor)
Prof. Kotresh Marali is a versatile teacher with 10+ years of experience. He is currently pursuing his P.hD in the field of Parallel Computing under the supervision of Dr. Sharada C. Sajjan. He has published around 12 research articles in National, International journals and conferences. He is Member for Association for Computing Machinery (ACM), Since 2020. Prof. Kotresh is good at MATLAB Scripting, Parallel Programming, Embedded C-Programming. He delivered technical talk on modern topics such as “Blockchain Technology”, “Embedded Systems”, “Automotive Electronics” etc. on different platforms.
Qualifications: M.Tech (Digital Electronics)
Phone Number: 944 977 0093
- Resource Person for Student Developmet Program (SDP) on “Exploring Pointers in C”, organised by Department of E&CE, SDM College of Engineering and Technology, Dharwad, Karnataka from 28th to 31st July 2020. (Online Mode)
- Resource Person for short-term training program on “Exploring Pointers in C”, organised by Department of E&CE, Hirasugar Institute of Technology, Nidasoshi, Karnataka from 16th to 20th July 2020. (Online Mode)
- Resource Person for two days workshop on “MATLAB and SIMULINK”, organised by Department of Electronics, Karnataka University, Dharwad, held on 21st & 22nd February 2019.
- Course Instructor for Automotive Electronics suggested by KPIT Technologies which is has been thought for placed students as per the MOU with SDMCET.
- Invited as a resource person at BEC Bagalkote to deliver a talk on “Model Based Software Engineering using MATLAB & SIMULINK” which was held on 19th March 2016.
- Resource Person for “Basic Electronics for Mechatronics” for students of Mechanical Engineering which was held during February 2016.
- Resource person for two-day workshop on “Automotive Electronics- A Hands-on Session” on 6th & 7th February 2015 for 8th & 6th semester students of E&CE and E&EE branch at SDMCET, Dharwad.
- Resource Person for “Introduction to MATLAB” for students of all Engineering branches which was held during 2015-2016 organized by Center for Industry Institute cell, SDMCET, Dharwad.
- Resource Person for “Model Based Design Using MATLAB & SIMULINK” for students of all Engineering branches which was held during 2015-2016 organized by Center for Industry Institute cell, SDMCET, Dharwad.
- Resource person for a one-day training program on “Microcontrollers and Interfacing”, held on 4th of April 2015, organized by Department of E&CE. (An Initiative of in house training Program).
Prof. Channakka Anand Kolu (Assistant Professor)
Prof. Channakka A. Kolur is working as Assistant Professor in the department of Electronics and Communication Engineering at SDM College of Engineering and Technology, Dharwad, Karnataka, INDIA. She obtained her Bachelor of Engineering from SDMCET, Dharwad., Karnataka. M Tech in Digital Electronics from SDMCET, Dharwad, Karnataka. She has Guided U.G. and PG students. Actively involved in Conduction of 01 National Conference and various workshops.
Qualifications: B. E., M. Tech
- Design, Implementation and Analysis of Flash ADC architecture with Differential Amplifier as Comparator using Custom Design Approach” at International Journal of Electronics Signals and Systems (IJESS) ISSN, Volume 1, Year 2012, Pages 2231—5969.
- 8 Point DFT Computation using Butterfly structure on Vertex kit in Bonfring International Journal of Research in Communication Engineering Bonfring International Journal of Research in Communication Engineering , Volume 6, pp 99-102; https://doi.org/10.9756/bijrce.8211
- International Journal of Advance Research in Engineering, Science & Technology e-ISSN: 2393-9877, p-ISSN: 2394-2444 Volume 3, Issue 5, May-2016 All Rights Reserved, @IJAREST-2016 420 Impact Factor (SJIF): 3.632. IMPLEMENTATION OF ADVANCED ENCRYPTION STANDARD IN SIMPLE, COMPOSITE AND EXTENDED MODE
- Design, Simulation and Power Analysis of Sigma-Delta Modulator using 0.18μm CMOS Technology in International Journal of Current Engineering and Technology
Phone Number: 991 619 7347
- Completed the course Information Theory, Coding and Cryptography with the Elite certificate.
- Best certificate award for a paper Analysis of different approaches for Dynamic Power Dissipation in Digital Circuit in AICTE Sponsored e-conference on Cutting Edge Technologies in Electrical, Communication, Embedded System and Soft Computing Techniques (ICECES 2020) organised by Saranathan College of Engineering 2020.
- Traning sessions for students who are eligible for KPIT.
- worked as Session Chair for the Technical sessions – I & II, during the International Conference on Electrical and Communication Engineering (ICECE)-2012, organized by Interscience Research Network-IRNET, Orissa on 29th July 2012.
Prof. J. V. Sangeetha Goud (Assistant Professor)
Qualifications: M. Tech, MBA
Phone Number: 827 718 6864
Prof. Reshma Nadaf (Assistant Professor)
Reshma Nadaf is working as Assistant Professor in the department of Electronics and Communication Engineering since 2007. She obtained B.E from STJ Institute of Technology and M.Tech in Digital Electronics from KLSGIT, Belagavi. Currently she is pursuing her PhD from from VTU. Her field of interests are Cryptography, ARM Processor, Computer Communication Networks , HDL programming and Embedded systems. She has guided more than 15 UG projects and more than 5 PG projects. She has conducted various workshops and FDPs and published more than 8 papers at National and International Conferences. Member of IEEE and IETE.
Qualifications: B. E., M. Tech, Ph. D
- Keerthi S, Reshma Nadaf, “ Hiding Text in a Video using Frequency domain and Time domain”, “SAMRIDDHI” , A Journal of Physical Sciences, Engineering and Technology, ISSN (P) : 2229-7111, Volume 12, Special issue 3, pp 157-162. 2020, doi.org/10.18090/samriddhi.v12iS3.30.
- Keerthi S, Reshma Nadaf, “ Hiding Text in a Video using Frequency domain and Time domain”, 8th International Conference on Innovations in Electronics and Communication Engineering, Springer ,2-3 August 2019.
- Reshma Nadaf, “Area Efficient Implementation of Secure Hash Algorithm-1 using Reconfigurable Architecture”, 4th IEEE International Conference for Convergence in Technology, 27-28 October 2018.
- Sana Bellary, Reshma Nadaf, “ Securing data from cyber crime using combination of SHA-1 and RSA algorithm”, International Journal of Advanced Scientific Technologies in Engineering and Management Sciences, ISSN:2454-356X, Volume 4, Issue 7, July 2018.
- Sachin Aralikatti, Reshma Nadaf, “ High Speed Implementation of Floating Point Multiplier for low Power Design Applications”, Bonfring International Journal of Research in Communication Engineering , ISSN : 2277-5080, Volume 6, Special Issue , November 2016. DOI: 10.9756.
- Sachin Aralikatti, Reshma Nadaf, “ An Efficient Implementation of 32-bit binary Multiplier for High Speed Design Applications”, International Journal of Engineering and Management Research, ISSN : 2250-0758, Volume 6, Issue-2 , March- April 2016.
- Riyaz Ahammad Nadaf, Reshma Nadaf, “Implementation of Image Steganography and Comparative Study of different Stegnographic Techniques”, International Journal of Advance Research in Engineering, Science and Technology, ISSN : 2393-9877, Volume 2, Issue -4, April 2015.
- Md. Shoaibuddin Madni, Reshma Nadaf, “ Color Recognition for Sixth Sense Device” , IEEE National Conference on Electronics , Communication and Advanced Networks, 21 June 2013.
- Reshma Nadaf, Veena Desai, “ Hardware Implementation of Modified AES with key dependent Dynamic S-box”, IEEE International Conference on Advanced Research in Engineering and Technology, 8-9 February 2013.
Phone Number: 974 227 1757
- Received funding from IEEE under Student Humanitarian Technology Project funding 2021.
- VTU sponsored student project under ” AVISHKAR” scheme in 2020.
- Faculty Advisor for IEEE CAS SB Chapter.
Prof. Preeti Shivayya Bellerimath (Assistant Professor)
Myself Preeti Bellerimath keen to teach and motivate students to gain knowledge in various field.My field of Interest is VLSI.
Qualifications: M. Tech, Ph. D
- International and National Conferences/ Journals = 7
Phone Number: 990 227 3217
Prof. Shrikanth Shirakol (Assistant Professor)
Prof. Shrikanth Shirakol is working as Assistant Professor in the department of Electronics and Communication Engineering at SDM College of Engineering and Technology, Dharwad, Karnataka, INDIA. He obtained his Bachelor of Engineering from KVGCE, D.K., Karnataka. M Tech in Microelectronics and Control Systems from N.M.A.M.I.T, Nitte, Karnataka. He is pursuing Ph.D. from VTU, Belagavi, Karnataka, India. He has Guided 15+ U.G. and 5+ PG students. Actively involved in Conduction of 01 National Conference and various workshops. He was Resource person for various value added training programs such as Pointers in C, MATLAB, VLSI design, FPGA. Published 4 papers at International Journal and 5 at conferences and he is life member of various professional societies like IETE, ISTE, IEI. His research interests are VLSI architectures for Image processing algorithms, Embedded Systems.
Qualifications: B. E., M. Tech
- FPGA-Based Implementation of Digital Filters for Image De-noising” at Lecture Notes in Electrical Engineering, Volume 750, Year 2021, Pages 155-166. (Scopus indexed)
- “Performance optimization of dual stage algorithm for lossless data compression and decompression” at International Journal of Engineering and Technology (UAE), Volume 7, Year 2018, Pages 127-130. (Scopus indexed)
- “Edge Detection Algorithm Using PI-Computer” at Bonfring International Journal of Research in Communication Engineering, Volume 6, Year 2016, Pages 79-82.
- “Design and Synthesis of Systolic Array Architecture for Matrix Multiplication” at International Journal of Engineering and Management Research (IJEMR), Volume 6, Year 2016, Pages 717-721.
- “Design and implementation of 16-bit carry skip adder using efficient low power high performance full adders” at Emerging research in Computing, Information, Communication and Applications: ERCICA-2014, volume 2, ISBN: 9789351072621, Paper ID: 118, Year 2014, Pages 782—790.
- “A Decimal Floating Point Arithmetic Unit for Embedded System Applications using VLSI Techniques” at International Journal of Engineering Trends and Technology (IJETT), Volume 12, Year 2014, Pages 365-370.
- “Design, Implementation and Performance Analysis of 1-Bit CMOS Full Adder using GDITL” Emerging research in Computing, Information, Communication and Applications: ERCICA-2014, volume 2, ISBN: 9789351072621, Paper ID: 65, Year 2014.
- “Design, Implementation and Analysis of Flash ADC architecture with Differential Amplifier as Comparator using Custom Design Approach” at International Journal of Electronics Signals and Systems (IJESS) ISSN, Volume 1, Year 2012, Pages 2231—5969.
- “Design and FPGA Implementation of 2D-DCT using Distributed Arithmetic” at 47th ISTE National Annual Convention at Saintgits College of Engineering, Kottayam, Kerala during 27 – 29 January 2018.
- “Design and Implementation of 1-D DCT using VLSI Technique” in 3rd International Conference on Electronics and Communication Systems (ICECS) which was held on Feb 23rd and 24th, 2016.
- “Real time Image monitoring and Control system using CPLD” at Conference on Evolutionary trends in Information Technology (CETIT 2011) held at VTU, Belgaum on 20th – 22nd May 2011.
Phone Number: 988 605 9174
- Qualified National Entrance Test (NET) in the year 2015
- Value addition Training programs conducted:
- Pointers in C
- Introduction to MATLAB
- Refresher Courses to support students for their GATE Preparation
Dr. Vyas R Murnal (Assistant Professor)
Dr.Vyas R Murnal completed his BE in Electronics and Communication Engineering from Rural Engineering College, Hulkoti in the year 2006. He then worked in a reputed IT Services Company in Hyderabad from 2007 to 2009 on Microsoft .NET technologies. Later he completed his M.Tech (Nanotechnology) from VIT Vellore in the year 2012. Dr.Vyas R Murnal joined the Department of ECE, SDMCET as an Assistant Professor in the year 2012. He completed his Ph.D in the year 2020 from VTU Belgaum. His research interests are Semiconductor Device Physics, CMOS VLSI, Nanoelectronics and MEMS. He has published many research articles in reputed international journals and conferences. Dr.Vyas R Murnal is passionate about both teaching and research. He his a life time member of IE and ISTE.
Qualifications: B. E., M. Tech, Ph. D
- A quasi-ballistic drain current, charge and capacitance model with positional carrier scattering dependency valid for symmetric DG MOSFETs in nanoscale regime https://link.springer.com/article/10.1186/s40580-019-0189-y
- AN IMPROVED NANOSCALE QUASI-BALLISTIC DOUBLE GATE (DG) MOSFET MODEL WITH DRAIN BIAS DEPENDENCY ON CRITICAL CHANNEL LENGTH NEAR THE LOW FIELD SOURCE REGION BY SEMI-EMPIRICAL Approach http://ictactjournals.in/paper/IJME_Vol_6_Iss_4_Paper_4_1020_1026.pdf
- Comparative Analysis of Diverse Carrier Transports in Multigate MOSFETS under different Channel Length Regimes http://ictactjournals.in/paper/IJME_Vol_7_Iss_3_Paper_3_1171_1177.pdf
- An Analytic Potential Based Velocity Saturated Drain Current, Charge and Capacitance Model for Short Channel Symmetric Double Gate MOSFETs https://link.springer.com/chapter/10.1007/978-981-15-5558-9_63
- A Quasi-Ballistic Drain current model with Positional Scattering Dependency applicable for Nanoscale DG MOSFETs https://ieeexplore.ieee.org/abstract/document/8869340/
- Measurement of light luminance and temperature monitoring for real time energy saving applications using Arduino Uno Atmega328 http://www.journal.bonfring.org/papers/rce/volume6/BIJ-8196.pdf
Phone Number: 888 427 7007
- Received Best Paper Award – 2019, VSPICE-2019 International Conference held at NMAM Institute of Technology, Nitte.
- Qualified in GATE 2013.
- Received Merit Scholarships during M.Tech (2011 & 2012) at VIT University, Vellore
- Received Rajya Puraskar Award in Scouts – 1999 from (The Bharat Scouts and Guides)
- Topper in CBSE Tenth Board Exams at JNV Belgaum (2000)
Prof. Raghuram K M (Assistant Professor)
Area of Interest are 1. Analog and Digital Circuits, Digital Signal Processing, Automotive Electronics, Wireless Sensor Networks, Computer Communication Networks, Multimedia Communication
Qualifications: B. E., M. Tech, Ph. D
- Performance Analysis of Fault Identification and Recovery in MANET”, International Journal of Engineering Research in Electronics, Vol 5, Issue 5, May 2018.
- Data Acquisition and Analysis from Sensors to Cloud”, International Journal Of Engineering Research & Technology, 2018
Phone Number: 948 145 0177
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